1. Field of the Invention
The present invention relates to multi-function timing sequencers of the type employed in mainframe multi-processor systems. More particularly, the present invention relates to a novel timing sequencer having a plurality of selectable sequence signals adapted to coordinate the interface logic between an instruction processor and a main storage unit (MSU) having different access speeds.
2. Description of the Prior Art
Heretofore, timing circuits and sequencers were known and are classified in International Class HO3K, Subclass 21/40 and in U.S. Class 377, Subclasses 39, 52 and 70+.
Sequencers provide a sequence of clocked signals for coordinating a series of steps, functions or events in a computing system which together provide means for accomplishing specific functions or commands. In contrast thereto, timing generators or clock circuits provide a sequence of related time clocked signals and generally employ major and minor clocked cycles having subdivisions or phases which are for general purpose and are used throughout the computing system.
Heretofore, sequencers were designed to accomplish specific functions, such sequencers were usually constructed employing a plurality of flip-flops in a series chain which were clocked by timing signals to produce a series of signals used for gating functions. Sequencers have employed real time signals which are used as the input to decoders to further produce the desired gating signals but such structure is usually involved in more complex circuitry and logic delays.
U.S. Pat. No. 4,756,013 shows and describes a "Multi-Function Counter/Timer" which combines the above-mentioned counter, timing circuits with comparators, decoder qualification circuits and an output buffer register which results in a signal or a plurality of signals at the occurrence of a predetermined data event. Such timers are not sequencers and require more complex circuitry than sequencers.
It would be desirable to provide a multi-function sequencer which employs the minimum circuitry and minimum logic delays for use in a high speed mainframe multi-processor computing system.